Volume 2, Number 1 (2019)
Year Launched: 2016
Journal Menu
Archive
Previous Issues
Why Us
-  Open Access
-  Peer-reviewed
-  Rapid publication
-  Lifetime hosting
-  Free indexing service
-  Free promotion service
-  More citations
-  Search engine friendly
Contact Us
Email:   service@scirea.org
Home > Journals > SCIREA Journal of Electrics, Communication > Archive > Paper Information

Realization of a Low Power and Area-Efficient VLSI Architecture for Carry Select Adder using Multiplexer Based Adders

Volume 2, Issue 1, February 2019    |    PP. 19-38    |PDF (775 K)|    Pub. Date: May 5, 2019
72 Downloads     344 Views  

Author(s)
Bala Sindhuri Kandula, Department of Electronics and communication Engineering, University College of Engineering,JNTUK,Kakinada, India
K.Padma Vasavi, SVECW, Bhimavram, India
I.Santi Prabha, Department of Electronics and communication Engineering, University College of Engineering,JNTUK,Kakinada, India

Abstract
Carry Select Adder (CSLA) is the most popular choice for multiply and accumulate operations because of its high performance in fast computations. However, the major drawback for CSLA is resource utilization as it occupies more area and power when compared to Ripple Carry Adder (RCA). Low Power and area efficiency can be achieved by using multiplexer based adders as the switching activity reduces the resource utilization. The proposed architecture is designed by using two bit adders using 4:1 multiplexers and synthesized in cadence RTL compiler using 90nm technology. The performance evaluation of the proposed architecture in terms of area and power is compared with Square Root Carry Select Adder (SQRT CSLA), Square Root Carry Select Adder using Kogge-stone Adder (SQRT-KSA), Square Root Carry Select Adder using Binary to Excess-1 Converter (SQRTCSLA-BEC),Kogge-stone Square Root Carry Select Adder using Binary to Excess-1 Converter (SQRTKSA-BEC)architectures for different bit depths ranging from 16 bits to 64 bits. The Proposed architecture is proved to be efficient both in terms of area and power when compared to SQRTCSLA, SQRT-KSA, SQRTCSLA-BEC, SQRTKSA-BEC architectures

Keywords
Carry Select Adder (CSLA), Multiplexer Based Adder,Area and Power Efficient, Two Bit Adder.

Cite this paper
Bala Sindhuri Kandula, K.Padma Vasavi, I.Santi Prabha, Realization of a Low Power and Area-Efficient VLSI Architecture for Carry Select Adder using Multiplexer Based Adders, SCIREA Journal of Electrics, Communication. Vol. 2 , No. 1 , 2019 , pp. 19 - 38 .

References

[ 1 ] R. W. Stewart et al., ‘‘A low-cost desktop software defined radio design environment using MATLAB, simulink, and the RTL-SDR,’’ IEEE Commun. Mag., vol. 53, no. 9, pp. 64–71, Sep. 2015. DOI: 10.1109/MCOM.2015.7263347
[ 2 ] XIN CAI , MINGDA ZHOU ,XINMING HUANG “ Model-Based Design for Software Defined Radio on an FPGA”.pp.8276-8283,vol.5,IEEEACCESS, DOI: 10.1109/ACCESS.2017.2692764
[ 3 ] N. Kumar, K. R. Nalluri and G. Lakshminarayanan, "Design of area and power efficient digital FIR filter using modified MAC unit," 2015 2nd International Conference on Electronics and Communication Systems (ICECS) Pp: 884 – 887, DOI: 10.1109/ECS.2015.7125041.
[ 4 ] A. P. Vinod, E. M-k. Lai, S. Emmanuel “Low power and high-speed implementation of FIR filters for software defined radio receivers”, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications,  DOI:10.1109/PIMRC.2006.254369.
[ 5 ] S. Mirzaei, A. Hosangadi and R. Kastner, “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method”. In IEEE Proc. International Conference on Computer Design, San Jose, CA, pp. 308- 313, Oct. 2006,DOI: 10.1109/ICCD.2006.4380833.
[ 6 ] R. I. Hartley, “Subexpression sharing in filters using canonical signed digit multipliers”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 677-688, 1996, DOI: 10.1109/82.539000.
[ 7 ] R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova, “A new algorithm for elimination of common subexpressions”, IEEE Trans. Computer-Aided Design, vol. 18, no. 1, pp .58-68, 1999, DOI: 10.1109/43.739059.
[ 8 ] C. Y. Yao, H. H. Chen, C. J. Chien and C. T. Hsu, “A novel common subexpression elimination method for synthesizing fixed point FIR filters”, IEEE Trans. Circuits Syst. I, vol. 51, no. 11, pp. 2215-2221, 2004, DOI: 10.1109/TCSI.2004.836853.
[ 9 ] Abhijit Chandra , Sudipta Chattopadhyay “Design of hardware efficient FIR filter: A review of the state-of-the-art approaches” Engineering Science and Technology, an International Journal,pp.212-226. University. http://dx.doi.org/10.1016/j.jestch.2015.06.006.
[ 10 ] K. Muhammad and K. Roy, “A graph theoretic approach for synthesizing very low-complexity high-speed digital filters”, IEEE Trans. Computer-Aided Design, vol. 21, no. 2, pp. 204-216, 2002, DOI: 10.1109/43.980259.
[ 11 ] O. Gustafsson and L. Wanhammar, “A novel approach to multiple constant multiplication using minimum spanning tree”. In Proc. IEEE Mediterranean Electrotechnical Conf., Dubrovnik, Croatiamum spanning trees”. In Proc. IEEE Midwest Symp. Circuits Syst., Tulsa, OK, vol. 3, pp. 652-655, 2002, DOI: 10.1109/MWSCAS.2002.1187124.
[ 12 ] H. Ohlsson, O. Gustafsson and L. Wanhammar, “Implementation of low-complexity FIR filters using a minimum spanning tree”. vol. 1, pp. 261-264, May 2004, DOI: 10.1109/MELCON.2004.1346826.
[ 13 ] G. Dempster and M. D. Macleod, “Use of minimum-adder multiplier blocks in FIR digital filters”, IEEE Trans. Circuits Syst.-II, vol. 42, no. 9, pp. 569-577, 1995, DOI: 10.1109/82.466647.
[ 14 ] Parhami, Computer Arithmetic, Algorithms and hardware Designs, Oxford University.Press, London, U.K, 2000.
[ 15 ] H. R. Lee. C. W. Jen, and C. M. Liu, “A new hardware-efficient architecture for programmable FIR filters”, IEEE Trans. Circuits Syst. II, vol. 43, no. 9, pp. 637-644, 1996, DOI: 10.1109/82.536760.
[ 16 ] S. Mitra, L. J. Avya and E. J. McCluskey, "Efficient multiplexer synthesis techniques," in IEEE Design & Test of Computers, vol. 17, no. 4, pp. 90-97, Oct.-Dec. 2000. doi: 10.1109/54.895009
[ 17 ] M. Faust and C. H. Chang, “Minimal logic depth adder tree optimization for multiple constant multiplication”. In Proc. IEEE Int. Symp. On Circuits Syst.(ISCAS), Paris, France, pp. 457-460, June 2010, DOI: 10.1109/ISCAS.2010.5537658.
[ 18 ] Anubhuti Mittal; Ashutosh Nandi; DishaYadav “Comparative study of 16-order FIR filter design using different multiplication techniques”  IET Circuits, Devices & Systems,pp.196-200,Issue-3,2017, DOI: 10.1049/iet-cds.2016.0146.
[ 19 ] Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung “A novel multiplexer based low power full adder” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 7, JULY 2004, DOI: 10.1109/TCSII.2004.831429.
[ 20 ] B.Ram kumar,Harish M kittur “Low power and area efficient carry select adder”pp.371-375,  IEEE Transactions on Very Large Scale Integration (VLSI) Systems ,Volume: 20, Issue: 2, Feb. 2012, DOI: 10.1109/TVLSI.2010.2101621.
[ 21 ] K.Bala Sindhuri; N.Udaya Kumar; A.Durga Prasad; K.V.S.S.Lalitha Siva Jyothi,”Area Efficient VLSI Architecture for square root Carry Select Adder using Kogge-Stone Adder and Binary to Excess-1 Converter” 2017 Innovations in Power and Advanced Computing Technologies (i-PACT)

Submit A Manuscript
Review Manuscripts
Join As An Editorial Member
Most Views
Article
by Sergey M. Afonin
2903 Downloads 16159 Views
Article
by Syed Adil Hussain, Taha Hasan Associate Professor
2246 Downloads 14812 Views
Article
by Omprakash Sikhwal, Yashwant Vyas
2316 Downloads 13721 Views
Article
by Munmun Nath, Bijan Nath, Santanu Roy
2222 Downloads 13639 Views
Upcoming Conferences
Jul.
17