An important relation between threshold voltage and the density of interfacial defect states in Poly-Si TFTs
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Author(s)
Abstract
Interface defect states of polycrystalline silicon thin-film transistors (poly-Si TFTs) play important role in the degradation of subthreshold characteristics. In this paper, an investigation of interface states is taken on, results show that both the threshold voltage and the difference between the threshold voltage and the gate voltage corresponding to the minimum drain current are proportional to the density of interface states at the SiO2/poly-Si interface, and results fit well with the experimental data.
Keywords
poly-Si, thin film transistor, interface defect states
Cite this paper
Lei Qiang,
An important relation between threshold voltage and the density of interfacial defect states in Poly-Si TFTs
, SCIREA Journal of Physics.
Volume 5, Issue 5, October 2020 | PP. 100-107.
References
[ 1 ] | D. C. Moschou, G. P. Kontogiannopoulos, D. N. Kouvatsos, and A. T. Voutsas, "On the importance of the V(g.max)-V(th) parameter on LTPS TFT stressing behavior," Microelectronics Reliability, vol. 50, pp. 190-194, Feb 2010. |
[ 2 ] | T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, K. Ono, and N. Konishi, "An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits," International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), 01 1993. |
[ 3 ] | Y. J. Yun, B. G. Jun, Y. K. Kim, J. W. Lee, and Y. M. Lee, "Design of system-on-glass for poly-Si TFT OLEDs using mixed-signals simulation," Displays, vol. 30, pp. 17-22, Jan 2009. |
[ 4 ] | N. C. C. Lu, L. Gerzberg, C. Y. Lu, and J. D. Meindl, "A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon films," IEEE Transactions on Electron Devices, vol. ED-30, Feb. 1983. |
[ 5 ] | T. Chow and M. Wong, "An Analytical Expression for the Transfer Characteristics of a Polycrystalline Silicon Thin-Film Transistor With an Undoped Channel," IEEE Transactions on Electron Devices, vol. 56, pp. 1493-1498, Jul 2009. |
[ 6 ] | M. Kimura and C. Dimitriadis, "Dependence of off-leakage current on channel film quality in poly-Si thin-film transistors and analysis using device simulation," Solid-State Electronics, vol. 57, pp. 87-89, Mar 2011. |
[ 7 ] | M. Wong, T. Chow, C. C. Wong, and D. L. Zhang, "A quasi two-dimensional conduction model for polycrystalline silicon thin-film transistor based on discrete grains," IEEE Transactions on Electron Devices, vol. 55, pp. 2148-2156, Aug 2008. |
[ 8 ] | T. S. Li and P. S. Lin, "On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size," Ieee Electron Device Letters, vol. 14, pp. 240-242242, May 1993. |
[ 9 ] | M. D. Jacunski, M. S. Shur, and M. Hack, "Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs," IEEE Transactions on Electron Devices, vol. 43, pp. 1433-14401440, Sept. 1996. |
[ 10 ] | R. Shringarpure, S. Venugopal, L. T. Clark, D. R. Allee, and E. Bawolek, "Localization of gate bias induced threshold voltage degradation in a-Si : H TFTs," Ieee Electron Device Letters, vol. 29, pp. 93-95, Jan 2008. |
[ 11 ] | S. D. Liu and S. C. Lee, "Large grain poly-Si (similar to 10 mu m) TFTs prepared by excimer laser annealing through a thick SiON absorption layer," IEEE Transactions on Electron Devices, vol. 51, pp. 166-171, Feb 2004. |
[ 12 ] | Y. Zhou, M. Wang, D. Zhou, D. Zhang, and M. Wong, "An Analytical Expression for Threshold Voltage of Polycrystalline-Silicon Thin-Film Transistors," Ieee Electron Device Letters, vol. 31, pp. 815-817, Aug 2010. |
[ 13 ] | D. M. Caughey and R. E. Thomas, " Carrier mobilities in silicon empirically related to doping and field," vol. 55, p. 2193, 1967. |
[ 14 ] | G. Y. Yang, S. H. Hur, and C. H. Han, "A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation," IEEE Transactions on Electron Devices, vol. 46, pp. 165-172, Jan 1999. |
[ 15 ] | D. H. Redinger, "Lifetime Modeling of ZnO Thin-Film Transistors," IEEE Transactions on Electron Devices, vol. 57, pp. 3460-3465, Dec 2010. |